VHDL History

History :

VHDL is an acronym for very high speed integrated circuit language (VHSIC) hardware description language (HDL). VHDL is used to describe the logical structure and functions of digital systems that are varying from simple gates to complex PLDs (FPGAs, ASICs). It facilitates design specification and simulation of digital systems. Even though initially it was not meant for synthesis, it can be used for synthesis within a limited domain. 

It was initiated by the US Department of Defense in the 1980s as a need for a standard HDL for their projects as different vendors were using different languages for IC design. In 1981, three companies —IBM, Texas Instruments and Intermetrics—were entrusted with the job of developing a common standard language for design, and VHDL was proposed as the high description language.Presently, Verilog and VHDL are two design HDLs used widely.

Design :

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.
VHDL is strongly typed and is not case sensitive.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. 
It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.

Advantages:

The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system.

A VHDL project is portable.

Disadvantages:

lack of analog support.

VHDL Simulators available:

Commercial:
Aldec Active-VHDL
Cadence Incisive 
Mentor Graphics ModelSim.
Synopsys VCS
Xilinx Vivado 

Other:
GHDL and GTKWave
Simili