Shift Operators in VHDL

vect   = 1 0 X 1 Z       
result  = 0 0 0 0 0 (initialized to 0)

SLL : (Shift Left Logical)

  result <= vect sll 1  
  output :  vect  = 1 0 X 1 Z  
               result = 0 X 1 Z 0  
  In SLL LSB bit is filled 0.   

SRL : (Shift Right Logical)  

    result <= vect srl 1  
  output :  vect    = 1 0 X 1 Z   
               result   = 0 1 0 X 1  
      In SRL MSB bit is filled 0.  

SLA : (Shift Left Arithmetic)

  Example 1.  
    result <= vect sla 1  
    output :   vect    = 1 0 X 1 Z  
                  result   = 0 X 1 Z Z  
     In SLA LSB bit is replicated.  
 Example 2.  
    result <= vect sla 2  
    output :  vect   = 1 0 X 1 Z  
                 result  = X 1 Z Z Z  
    In SLA LSB bit is replicated twice (ie.,no of shifts).  

SRA : (Shift Right Arithmetic)

   Example 1.  
     result <= vect sra 1  
     output : vect   = 1 0 X 1 Z  
                 result  = 1 1 0 X 1  
     In SRA MSB bit is replicated.  
  Example 2.  
     result <= vect sra 2  
     output : vect   = 1 0 X 1 Z  
                 result  = 1 1 1 0 X  
     In SRA MSB bit is replicated twice (ie.,no of shifts).  

ROL : (Rotate Left)

    result <= vect rol 2  
  output : vect   = 1 0 X 1 Z  
              result  = 1 Z 1 0 X  

ROR : (Rotate Right)

    result <= vect ror 2  
  output : vect   = 1 0 X 1 Z  
              result  = X 1 Z 1 0  

More Examples :

Example 1. 
    vect   = 0 1 1 0  -> (6)
    result = 0 0 0 0  -> (initializedto 0)
    All are Shift by 1 unit operation.

    SLL :
    vect SLL 1        result       actualResult
    (mul by 2)
    1 1 0 0           12(C)          12
    1 0 0 0           8 -error-      24 
    0 0 0 0           0                0
   
    SLL does multiplication operation by 2^(no.Shifts).In case of error in multiplication result add a correction bit of 2^(n-1) (where n is no. of bits needed for representing the actual result) at MSB.
   i.e., 2^4 * 1+ 2^3 * 1 + 0 + 0 + 0  = 24 is the actual result.

    SRL :
    vect SRL 1        result       actualResult
    (div by 2)
     0 0 1 1          3               3
     0 0 0 1          1 -error-     1.5
     0 0 0 0          0               0

    SRL does Division operation by 2^(no.Shifts).In case of error in division result add (2^-m) (Where m is number of correction bit needed) at LSB to get the actual result. 
   i.e., 0 + 0 + 0 +1*2^0 + (2^-1) = 1 + 0.5 = 1.5 

Example 2.
   vect   = 1 1 1 1  ->(15)
   result = 0 0 0 0  ->(initialized to 0)

   All are Shift by 1 unit operation.
   SLL :
   vect SLL 1    result   actual      #bits to Rep.      Binary Rep Of    
   (mul by 2)                   Result      Actual Result     Actual Result            
    1 1 1 0         14(E)    30          5 bits (0 -31)      1 1 1 1 0       
    1 1 0 0         12(C)    60          6 bits (0 -63)      1 1 1 1 0 0    
    1 0 0 0         8          120        7 bits (0-127)     1 1 1 1 0 0 0
    0 0 0 0         0          0           4 bits                 0 0 0 0

    #of Correction           Correction Bits
    Bits    
    5-4=1              2^4 *1 + 2^3 *1 + 2^2 *1 + 2^1 *1 + 0 = 30
    6-4=2              2^5 *1 + 2^4 *1 + 2^3 *1 + 2^2 *1 + 0 + 0 = 60
    7-4=3              2^6 *1 + 2^5 *1 + 2^4 *1 + 2^3 *1 + 0 + 0 + 0 = 120
    4-4=0              0 + 0 + 0 + 0 = 0

   SRL :
    vect SRL 1        result          actual        
    (div by 2)                               Result     
    0 1 1 1             7 (odd)      7.5      
    0 0 1 1             3 (odd)      3.75     
    0 0 0 1             1 (odd)      1.875    
    0 0 0 0            0               0   
  
    #of Correction                Correction Bits
     Bits=m       
    1     0 + 2^2 *1 + 2^1 *1 + 2^0 *1 +2^-1 *1 = 7.5
    2                  0 + 0 + 2^1 *1 + 2^0 *1 + 2^-1 *1 + 2^-2 *1 = 3.75
    3     0 + 0 + 0 + 2^0 *1 + 2^-1 *1 + 2^-2 *1 +2^-3 *1= 1.875
    0     0 + 0 + 0 +0 = 0