Gated D Latch

1.1.3  Gated D latch

  Block Diagram and Characteristic table :

Gated D latch

Working :

In the above figure ,we have a Gated SR Latch implemented using NAND gates.NAND implementation is used because will take less number on transistors.

The D input is given to S and D_bar ( ie.,NOT D) is given to R.Here we will not have the problem of latch going to forbidden state (ie., S=1 and R=1)

because inputs to this latch is reversed (ie., in SR latch first input is R and second is S but here it is reversed).

Lets Assume some value for the output Q (ie., 0 here) and proceed with it working.

  Q='0' , Clk='0' and D='x' :-         

                                               

  S'  =  Clk (nand) S

  R'  =  Clk (nand) R

  Q  =  Q_bar (nand) S'

  Q_bar =  Q (nand) R'

  Q= '0' assumed => Q_bar='1'
  

Q='0' , Clk='1' and D='0/1' :-

  S' =  Clk (nand) S

  R'=  Clk (nand) R

  Q =  Q_bar (nand) S'

  Q_bar =  Q (nand) R'

  Q= '0' assumed => Q_bar='1'

Table :
   Outputs for all combination of inputs and assumed values of Q.

 VHDL Code :

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
   
 entity D_Latch is  
   GENERIC (DELAY : time :=2 ns);  
   Port ( Din : in STD_LOGIC;  
          clock : in STD_LOGIC;  
                 Q : out STD_LOGIC;  
       Q_n : out STD_LOGIC);  
 end D_Latch;  
   
 architecture D_Latch_arch of D_Latch is  
 signal Q_tmp:STD_LOGIC;  
 begin  
  PROCESS (Din,clock)  
  BEGIN   
   if (clock = '1') then  
        Q_tmp <= Din after DELAY;  
       end if;  
  END PROCESS;  
 Q <= Q_tmp;  
 Q_n <= NOT Q_tmp;  
 end D_Latch_arch;  

 Waveform :

  2 ns of delay is kept in D-Latch.