Conversion Functions in VHDL

Conversion Functions in VHDL :-

Libraries To Include :
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

(1.) CONV_INTEGER() :- (use IEEE.std_logic_signed.all)
variable temp : integer:=0;
variable output : std_logic_vector(7 downto 0):=(others=>'0');
temp := CONV_INTEGER(output);
Output: temp = 0

(2.) CONV_STD_LOGIC_VECTOR () :- (use IEEE.std_logic_signed.all)
variable slv : std_logic_vector(7 downto 0);
variable temp : integer:=8;
slv = CONV_STD_LOGIC_VECTOR(temp,slv'LENGTH);
Output: slv = 00001000

(3.) INTEGER() and REAL() :-
variable t_real : real :=0.0;
variable temp_int : integer;
temp_int := INTEGER(t_real);
t_real := REAL(t_int);

(4.) SIGNED() and UNSIGNED() :-
signal a: std_logic_vector(7 downto 0);
signal a_sign: signed(7 downto 0);
signal a_unsign: unsigned(7 downto 0);
a_sign <= signed(a);
a_unsign <= unsigned(a);