SubType in VHDL

Syntax :-

subtype <subtype_name> is base_type range <range_constraint>;

Ex.1 )  subtype INT_16 is integer range –32768 to 32767;
        > subtype INT_16 is of type integer and range –32768 to 32767;
        > variable or signal defined of subtype can be assigned to a base type.

Ex.2) subtype SLV_16 is std_logic_vector(15 downto 0);

Ex.3) function ResolutionFunc (arrVal: int_arr) return integer;
        subtype resolvedINT is ResolutionFunc integer;
       > where int_arr is integer array type defined has
          type int_arr is array(0 to NATURAL'RANGE) of integer;
       > resolvedINT is the resolved integer type.