Concurrent Assignment statements

Ordering of the statements in vhdl code does not affect its meaning.Below is a simple example demonstrating concurrent assignment.

Example 1. 

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
   
 entity test123 is  
   Port ( enb_n: in std_logic;  
          f:out std_logic   
          );  
 end test123;  
 architecture test123_arch of test123 is  
 signal Atemp: std_logic;  
 signal stemp: std_logic;  
 begin  
       f <= '0'        WHEN enb_n='1' ELSE  
          not Atemp   WHEN stemp='0' ELSE   
          Atemp;        
      Atemp <= '1';  
      stemp <= '0';  
 end test123_arch;  

Output :

 f=0   Atemp=1   stemp=0  enb_n=0

This will not be a sequential assignment.Now if the statements are rearranged then output will be the same (because of concurrent assignment)

     Atemp <= '1';  
  stemp <= '0';  
  f <= '0'         WHEN enb_n='1' ELSE  
       not Atemp   WHEN stemp='0' ELSE   
       Atemp;  

Output :

 f=0  Atemp=1   stemp=0  enb_n=0

Types of Concurrent Assignments : 

 1.) Simple Signal assignemt. 
      Example :
        A.) B <= '1';
        B.) Z <= A1 xor A2 xor A3;
        C.) L <= not B;
 2.) Select Signal Assignment.
 3.) Conditional Assignment Statements.