SR Latch Working and Vhdl Code

1.1.1 Basic SR latch

         SR Latch is basic memory element used for data storage.No clock triggering is present for a Latch.SR latch is constructed using Cross Coupled NOR Gates. In the below diagram R and S are inputs and Q and Q_bar (is Not Q) are the outputs of SR-Latch.

Block Diagram and Characteristic table :

SR Latch

  

  

   

Working :

   A Latch is always level triggered. Here let's assume some value for output Q and validate the SR Latch characteristic table.

Here Q is assumed to be 0. 
                          

     Q='0' ,S='0' and R='0' :-

       Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='0'.

            Nor-Gate-2 Output  : Q_n='1'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='1' and R='0'.

          Nor-Gate-1 Output  : Q='0'

       So, for S='0' and R='0' the SR Latch Maintains its previous state.ie., No

       change in latch output.It acts has a storage element.

     Q='0' ,S='0' and R='1' :-

       Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='0'.

            Nor-Gate-2 Output  : Q_n='1'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='1' and R='1'.

          Nor-Gate-1 Output  : Q='0'

       So, for S='0' and R='1' the SR Latch RESETS the output(ie,.output is set 

       to 0).This is called reset operation and to be used for clearing latched 

       data.

     Q='0' ,S='1' and R='0' :-

        Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='1'.

            Nor-Gate-2 Output  : Q_n='0'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='0' and R='0'.

          Nor-Gate-1 Output  : Q='1'

       So, for S='1' and R='0' the SR Latch SETS the output(ie., output is set 
       to 1). 

     Q='0' ,S='1' and R='1' :-

        Nor-Gate-2 :

         Nor-Gate-2 Input     : Q='0' and S='1'.

           Nor-Gate-2 Output   : Q_n='0'

       Nor-Gate-1 :

         Nor-Gate-1 Input     : Q_n='0' and R='1'.

         Nor-Gate-1 Output   : Q='0'

      Here both Q and Q_n is set to same logic level that is 0 .This is a 
       restricted combination or a forbidden state and it should never occur,it breaks
      the logic equation Q_bar=NOT Q. 

      Say, previously S='1' and R='1' --> output is Q='0' and Q_n='0'.

      and now its changed to S='0' and R='0' --> output is Q='1' and Q_n='1'.

      But this new output values will be looped back to input side               
      and this changes the output back to Q='0' and Q_n='0'.So, the 
      output will be oscillating,this oscillation will continue indefinitely 
      and will finally settle down at logic value 0 or 1.

Table :-
    Outputs for all combination of inputs and assumed values of Q.

    

 VHDL Code :

 entity SR_Latch is  
  Port ( S,R : in STD_LOGIC;  
         Q : inout STD_LOGIC;  
         Q_n : inout STD_LOGIC);  
 end SR_Latch;  
   
 architecture SR_Latch_arch of SR_Latch is  
 begin  
 process (S,R,Q,Q_n)  
       begin  
             Q <= R NOR Q_n;  
             Q_n <= S NOR Q;  
       end process;  
   
 end SR_Latch_arch;