How to write VHDL test bench !!

step 1 :

Create a vhdl test bench file  Eg., counter_tb.vhd

step 2 :

Test bench will have a library declaration (standard  or user defined) ,  entity and an architecture.

entity body will be empty and Inside Architecture component under test is declared and port mapped.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY counter_tb IS
END counter_tb;

ARCHITECTURE counter_tb_arch OF counter_tb IS

-- component declaration --

-- procedure or function used by the architecture --

-- input , output and clock Signals are defined --

-- constants --
BEGIN

-- PORT MAP FOR THE UNIT UNDER TEST IS DONE --

-- PROCESS FOR CLOCK GENERATION --

-- PROCESS FOR OTHER INPUT SIGNALS GENERATION --

END;

Sample vhdl Nbit counter test bench code :-

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 use IEEE.std_logic_signed.all;  
 use IEEE.std_logic_arith.all;  
   
 ENTITY counter_tb IS  
 END counter_tb;  
   
 ARCHITECTURE counter_tb_arch OF counter_tb IS  
 -- component declaration for counter :START --  
 COMPONENT counter  
 GENERIC ( LEN:integer := 8 );  
 PORT(  
 clock : IN std_logic;  
 clr_n : IN std_logic;  
 enb_n : IN std_logic;  
 mode : IN std_logic;  
 load : IN std_logic;  
 datain : IN std_logic_vector(LEN-1 downto 0);  
 output : OUT std_logic_vector(LEN-1 downto 0)  
 );  
 END COMPONENT;  
   
 -- input , output and clock Signals are defined and initialized --  
 signal clock : std_logic := '0';  
 signal clr_n : std_logic := '1'; -- active low pin --  
 signal enb_n : std_logic := '0'; -- active low pin --  
 signal mode : std_logic := '0'; -- 0 :upcount , 1:downcount --  
 signal load : std_logic := '0'; -- 1 : load data --  
 constant cntrWidth : integer:= 8; -- counter width --  
 signal datain : std_logic_vector(cntrWidth-1 downto 0) := (others => '0'); -- data input --  
 signal output : std_logic_vector(cntrWidth-1 downto 0); -- output signal --  
 constant clkPeriod : time := 20 ns; --clock period --  
   
 BEGIN  
 -- PORT MAP FOR THE UNIT UNDER TEST IS DONE --  
 uut: counter generic map (LEN => cntrWidth) PORT MAP (  
 clock => clock,  
 clr_n => clr_n,  
 enb_n => enb_n,  
 mode => mode,  
 load => load,  
 datain => datain,  
 output => output  
 );  
   
 -- PROCESS FOR CLOCK GENERATION (50% duty cycle) --  
 clock_process :process   
 begin  
 clock <= '0';  
 wait for clkPeriod/2;  
 clock <= '1';  
 wait for clkPeriod/2;  
 end process;  
   
 -- PROCESS FOR OTHER INPUT SIGNALS GENERATION --  
 stim_proc: process  
 begin  
 wait for 100 ns; -- wait for output --  
 -- mode is set to 0 above ,so up count will happen from 0 to (2**N -1 )--  
 -- enb_n=0 so counter is enabled --  
 -- clr_n=1 so counter is not cleared when counting is started--  
 -- load=0 so no input data is loaded to counnter --  
 -- > IF You're using XILINX ISE   
 -- > then go to Simulation and select the test bench file   
 -- > RUN Simulate Behavioral Model.  
 -- > SIMLUATOR ( eg., MODEL-SIM ) will start up  
 -- > Now press RUN to get the output.  
   
 end process;  
 END;  

Nbit counter Output (N=8 here) :-