VHDL Component Declaration

SYNTAX :

  COMPONENT <component_name>  IS

      GENERIC (generic_list);

      PORT   (port_list);

  END COMPONENT <component_name>;


Component Declaration:
  
 A Component should be declared before using it.
  
 Where to Put ?
     Should be placed inside architecture block ,before begin statements.

      Architecture module1_arch of module1_ent is
      -- Component Declaration  here--
     begin

     end module1_arch ;

Component Instantiation or Mapping :

 After Declaring the component it should be port mapped. 

 Where to Put ?
   Should be placed inside architecture block ,after begin statements.

   Architecture module1_arch of module1_ent is
      
   begin
          -- Component Port Mapping here --
   end module1_arch ;



Example 1:

 entity module1_ent is  
   Port ( A : in STD_LOGIC;  
          B : in STD_LOGIC;  
          F : out STD_LOGIC );  
 end module1_ent;  
   
 Architecture module1_arch of module1_ent is  
 -- Component Declaration --  
 component XOR_2 is  
   port ( a : in std_logic;  
          b : in std_logic;  
          f : out std_logic  
         );  
 end component XOR_2;  
 begin  
 -- Component Port Mapping --   
  M1: XOR_2 port map ( A=> a ,B=> b,F=> f);  
 end module1_arch ;  

Example 2:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
   
 entity MasterSlaveDL is  
   Port ( Din : in STD_LOGIC;  
          clock : in STD_LOGIC;  
          Q_m : out STD_LOGIC;  
          Q_n_m : out STD_LOGIC);  
 end MasterSlaveDL;  
   
 architecture MasterSlaveDL_arch of MasterSlaveDL is  
 -- dlatch declaration --  
 component D_Latch is  
   GENERIC (DELAY : time :=2 ns);  
   Port ( Din : in STD_LOGIC;  
          clock : in STD_LOGIC;  
           Q : out STD_LOGIC;  
           Q_n : out STD_LOGIC);  
 end component D_Latch;  
 -- dlatch declaration --  
   
 -- Not Gate declaration --  
 component NotGate is  
   Port ( a : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component NotGate;  
 -- Not Gate declaration --  
   
 -- intermediate signals --  
 signal Q_s : STD_LOGIC;  
 signal Q_n_s : STD_LOGIC;  
 signal clockInv : STD_LOGIC;  
 -- intermediate signals --  
 begin  
   
       L2_inv : NotGate PORT MAP (clock,clockInv);   
         
       L1_slave : D_Latch GENERIC MAP(0 ns)  
                   PORT MAP (Din,clock,Q_s,Q_n_s);   
                        
       L3_master : D_Latch GENERIC MAP(0 ns)  
               PORT MAP (Q_s,clockInv,Q_m,Q_n_m);                                                 
 end MasterSlaveDL_arch;  

Basic Tcl commands-part3

For Tcl tutorial Part-1 click here
For Tcl tutorial Part-2 click here

TCL Info Command :

 puts "Hello World!"   
 set global-var  100  
 set son     "peter pan"  
   
 proc testing {arg1 arg2} {  
 # body :start  
 set i 11  
 puts [info locals]  
 puts [info proc testing]  
 puts "$arg1 $arg2"  
 puts "bye"  
 #body:end  
 }  
   
 testing 4 hshs  
 puts [info args testing]  
 puts [info body testing]  
 puts [info cmdcount]  
 puts [info commands]  
 puts [info commands puts]  
 puts [info globals]  
 puts [info globals global-var]  
 puts [info tclversion]  
 puts [info vars]  
 puts [info vars son]  
 puts [info hostname]  
 puts [info proc testing]  
   
 puts [info exists soninlaw]  
 puts [info exists son]  

puts [info args testing]
  -prints all the argument names of a procedure

 % arg1 arg2  

puts [info body testing]
  -prints the body of the procedure.

 % # body :start  
  set i 11  
  puts [info locals]  
  puts [info proc testing]  
  puts "$arg1 $arg2"  
  puts "bye"  
  #body:end  

puts [info cmdcount]
  -returns a count of the total number of commands that have been invoked in this interpreter.

 % 97  

puts [info commands]
   -returns a list of names of all the Tcl commands in the current namespace, including both the built-in commands and the command procedures defined using the proc command.

 %tell socket subst open eof pwd glob list pid exec testing auto_load_index time unknown eval lassign lrange fblocked lsearch auto_import gets case lappend proc break variable llength auto_execok return linsert error catch clock info split array if fconfigure concat join lreplace source fcopy global switch auto_qualify update close cd for auto_load file append lreverse format unload read package set binary namespace scan apply trace seek while chan flush after vwait dict continue uplevel foreach lset rename fileevent regexp lrepeat upvar encoding expr unset load regsub interp exit puts incr lindex lsort tclLog string  

puts [info commands puts]
   - returns tcl specific commands by pattern matching.If not matched null is returned.

 % puts  

puts [info globals]
 - returns a list of all the names of currently defined global variables.

 % tcl_rcFileName tcl_version argv0 argv tcl_interactive auto_path son env tcl_pkgPath tcl_patchLevel argc global-var tcl_library tcl_platf  

puts [info globals global-var]
  - search for specific global variable by pattern matching.

 % global-var  

puts [info tclversion]
  - displays the current tcl version number.

 % 8.5  

puts [info vars]
 - returns a list of all the names of currently visible variables.

 % tcl_rcFileName tcl_version argv0 argv tcl_interactive auto_path son env tcl_pkgPath tcl_patchLevel argc global-var tcl_library tcl_platf  

puts [info vars son]
 - returns a specific variable if pattern is matched otherwise null.

 % son  

puts [info hostname]
 - returns the hostname.

puts [info proc testing]
 - returns the procedure name if it exists else null.

 % testing  

puts [info locals]
 - returns all the local variables including procedure args.

 % arg1  arg2  i  

puts [info exists soninlaw]
 - if the variable (local or global) doesn't exists then return 0

 % 0  

puts [info exists son]
 - if the variable (local or global) exists then return 1.

 % 1  

info level :

 returns the stack level of invoking procedure.

 proc t2 {} {  
  puts "stack Level => [info level]"  
  }  
  proc t1 {} {  
   puts "stack Level => [info level]"  
   t2   
  }  
   
  #main#  
  puts "Main => [info level]"  
  t1   
  #main#  

output :

 % Main => 0  
  stack Level => 1  
  stack Level => 2  

Basic Tcl commands-part2

Tcl command Reference : http://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html
Online Tcl script editor :http://www.compileonline.com/execute_tcl_online.php

To check the tcl output please copy paste the below code in online tcl script editor and for more detailed explanation use the above reference .

For Tcl tutorial Part-1 click here

Conditions :

 set k  0
 puts "$k"

 % 0  

set result [ expr {($k == 0) ? "true":"false"} ] 
puts "$result"

 % true  

Increment :
set k 0
incr k
puts "k=$k"

 % k=1  

incr k 
puts "k=$k"

 % k=2  

incr k 10 
puts "k=$k"

 % k=12  

String Operations :-

String matching :
Syntax : string match <str1> <str2>
             matches the occurrence of str1 in str2.

set str1    "*=*"
set string1  "RUN_TIME = 1000"
puts  [string match $str1  $string1]

 % 1  

String first, last, compare :

compare :
compare performs a character by character comparison.
set string1    "this is sparta..."
set str1        "sparta"
puts [ string compare $string1 $str1 ]

 % 1  

puts [ string compare $str1 $string1 ]

 % -1  

puts [ string compare $string1 $string1 ]

 % 0  

If 1st string is greater than 2nd ,then return 1.
If 1st string is less than 2nd , then return -1 .
If 1st string is Equal to 2nd , then return 0.

first and last :
It will return the index position for first or last occurrence of a char or string.

set joker    "It's a funny world we live in. Speaking of which, do you know how I got these scars?"

puts [string first  "I"  $joker]
puts [string first  "a"  $joker]
puts [string first  "funny"   $joker]

 % 0  
 % 5  
 % 7  

puts [string last  "I"  $joker] 
puts [string last  "a"  $joker] 
puts [string last  "funny"  $joker]

 % 66  
 % 80  
 % 7  

Index :
Index returns a single character from string at index position number.

set xyz  "this is ...!"
puts  [ string index  $xyz  0 ]

 % t  

puts   [ string index $xyz 1 ]

 % h  

puts  [ string index $xyz end ]

 % !  

Range :
set  xyz      "this is ...!"
puts [ string range  $xyz  3  end ]

 % s is ...!   

tolower, toupper :
These arguments return a string made from the characters of string converted to the appropriate case.

tolower :
set  string1    "ToM RiDdLe"
puts [ string  tolower  $string1 ]

 % tom riddle  

toupper :
set  string1    "ToM RiDdLe"
puts [ string  toupper  $string1 ]

 % TOM RIDDLE  

String Length :

puts [ string length  "uzumaki naruto" ]

 % 16  

Split and Join Cmds :
set yyy  "din1 20 100,din2 40 80,din3 8 9,din4 25 40"

puts [ join [split $yyy ","] ]

 % din1 20 100 din2 40 80 din3 8 9 din4 25 40   

puts [ join [split $yyy ","] ":" ]

 % din1 20 100:din2 40 80:din3 8 9:din4 25 40  

Gated D Latch

1.1.3  Gated D latch

  Block Diagram and Characteristic table :

Gated D latch

Working :

In the above figure ,we have a Gated SR Latch implemented using NAND gates.NAND implementation is used because will take less number on transistors.

The D input is given to S and D_bar ( ie.,NOT D) is given to R.Here we will not have the problem of latch going to forbidden state (ie., S=1 and R=1)

because inputs to this latch is reversed (ie., in SR latch first input is R and second is S but here it is reversed).

Lets Assume some value for the output Q (ie., 0 here) and proceed with it working.

  Q='0' , Clk='0' and D='x' :-         

                                               

  S'  =  Clk (nand) S

  R'  =  Clk (nand) R

  Q  =  Q_bar (nand) S'

  Q_bar =  Q (nand) R'

  Q= '0' assumed => Q_bar='1'
  

Q='0' , Clk='1' and D='0/1' :-

  S' =  Clk (nand) S

  R'=  Clk (nand) R

  Q =  Q_bar (nand) S'

  Q_bar =  Q (nand) R'

  Q= '0' assumed => Q_bar='1'

Table :
   Outputs for all combination of inputs and assumed values of Q.

 VHDL Code :

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
   
 entity D_Latch is  
   GENERIC (DELAY : time :=2 ns);  
   Port ( Din : in STD_LOGIC;  
          clock : in STD_LOGIC;  
                 Q : out STD_LOGIC;  
       Q_n : out STD_LOGIC);  
 end D_Latch;  
   
 architecture D_Latch_arch of D_Latch is  
 signal Q_tmp:STD_LOGIC;  
 begin  
  PROCESS (Din,clock)  
  BEGIN   
   if (clock = '1') then  
        Q_tmp <= Din after DELAY;  
       end if;  
  END PROCESS;  
 Q <= Q_tmp;  
 Q_n <= NOT Q_tmp;  
 end D_Latch_arch;  

 Waveform :

  2 ns of delay is kept in D-Latch.