VHDL RANDOM Number Generation for testing

Create a package file func_pkg.vhd and copy paste the below code.

                                                "func_pkg.vhd"

 ----//START PACKAGE//-----  
 LIBRARY IEEE;  
 USE IEEE.std_logic_1164.ALL;  
 USE IEEE.std_logic_arith.all;  
 use IEEE.std_logic_signed.all;  
   
 package func_pkg is  
 shared variable seed1:integer:=844396720; -- uniform procedure seed1  
 shared variable seed2:integer:=821616997; -- uniform procedure seed2  
 impure function RANDOM_NUM_GEN(constant lower_value : in integer;  
 constant upper_value : in integer;  
 constant busWidth: in integer ) return integer;  
 end func_pkg;  
   
 package body func_pkg is  
 -------------------------------------------------------------------------  
 --- Function : RANDOM_NUM_GEN()  
 --- Args : lower_value ,upper_value and busWidth;  
 --- Library : USE work.func_pkg.all;  
 --- USE IEEE.std_logic_arith.all;  
 --- Task : The return value of this fn should be stored in  
 --- randomNum.So, each time new random value is assigned.  
 --- No PERIOD  
 -- stim_proc: process  
 -- begin  
 -- wait for 20 ns;  
 -- A <= CONV_STD_LOGIC_VECTOR(RANDOM_NUM_GEN(0,256,A'LENGTH),A'LENGTH);  
 -- B <= CONV_STD_LOGIC_VECTOR(RANDOM_NUM_GEN(10,200,B'LENGTH),B'LENGTH);  
 -- wait for WAIT_OP;  
 -- end process;  
 -------------------------------------------------------------------------  
 impure function RANDOM_NUM_GEN(constant lower_value : in integer;  
 constant upper_value : in integer;  
 constant busWidth: in integer ) return integer is  
 variable result : integer;  
 variable tmp_real : real; -- return value from uniform procedure --  
 begin  
 ASSERT (lower_value < (2**busWidth))  
 REPORT "RANDOM_NUM_GEN():lower_value Range is exceeded "  
 SEVERITY FAILURE;  
 ASSERT (upper_value < (2**busWidth))  
 REPORT "RANDOM_NUM_GEN():upper_value Range is exceeded"  
 SEVERITY FAILURE;  
 uniform(seed1,seed2,tmp_real);  
 -- generates rand no. inside busWidth limit --  
 result :=integer(trunc((tmp_real * real(upper_value - lower_value)) + real(lower_value)));  
 return result;  
 end RANDOM_NUM_GEN;  
 —-//END PACKAGE//—–  

How to use in TestBench : Inside architecture block (after begin statement) a testing process is added.Say ,A and B is a input bus of std_logic_vector(7 downto 0) .To generate a random number for each buses call the function RANDOM_NUM_GEN() and then call CONV_STD_LOGIC_VECTOR() to convert it to bit vector stream.

                                   "counter_tb.vhd"
USE work.func_pkg.all; -- library --
USE IEEE.std_logic_arith.all;
//Arch start
//begin
testing: process
begin
A <= CONV_STD_LOGIC_VECTOR(RANDOM_NUM_GEN(20,256,A'LENGTH),A'LENGTH;
B <= CONV_STD_LOGIC_VECTOR(RANDOM_NUM_GEN(55,200,B'LENGTH),B'LENGTH;
wait for WAIT_OP; --wait for 50 ns
end process;
//Arch end

Note :-
User defined function RANDOM_NUM_GEN( ) will generate NON PERIODIC and UNIQUE random number.
lower_value : starting range
upper_value : ending range
busWidth : width of the bus.
say, A is a bus of std_logic_vector(7 downto 0). Then random number should be generated from 0 to 255.
If lower_value or upper_value exceeds busWidth range i.e., 2^busWidth then failure is returned by the function and simulation is stopped .