Gated SR Latch Working and VHDL Code

1.1.2 Gated SR Latch

  Block Diagram and Characteristic table :

 

Working :  

Reference : For how SR latch works refer SR Latch.

  S -> set output to '1'

  R -> reset output to '0'

  Q(t)      -> present state.

  Q(t+1)  -> next state.

  Latch is always level triggered.

  When Clk='0' , R' and S' is 0 .So, No change in the output occurs.

  When Clk='1' , R and S inputs are propagated and its a basic SR latch

  operation.

  VHDL Code :               

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity Gated_SR_Latch is  
     Port ( S,R : in STD_LOGIC;  
          clock : in STD_LOGIC;  
          Q : inout STD_LOGIC;  
         Q_n : inout STD_LOGIC);  
 end Gated_SR_Latch;  
 architecture Gated_SR_Latch_arch of Gated_SR_Latch is  
 signal S_tmp:STD_LOGIC;  
 signal R_tmp:STD_LOGIC;  
 begin  
      S_tmp <= clock AND S;  
      R_tmp <= clock AND R;  
      Q <= R_tmp NOR Q_n;  
      Q_n <= S_tmp NOR Q;  
 end Gated_SR_Latch_arch;  

SR Latch Working and Vhdl Code

1.1.1 Basic SR latch

         SR Latch is basic memory element used for data storage.No clock triggering is present for a Latch.SR latch is constructed using Cross Coupled NOR Gates. In the below diagram R and S are inputs and Q and Q_bar (is Not Q) are the outputs of SR-Latch.

Block Diagram and Characteristic table :

SR Latch

  

  

   

Working :

   A Latch is always level triggered. Here let's assume some value for output Q and validate the SR Latch characteristic table.

Here Q is assumed to be 0. 
                          

     Q='0' ,S='0' and R='0' :-

       Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='0'.

            Nor-Gate-2 Output  : Q_n='1'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='1' and R='0'.

          Nor-Gate-1 Output  : Q='0'

       So, for S='0' and R='0' the SR Latch Maintains its previous state.ie., No

       change in latch output.It acts has a storage element.

     Q='0' ,S='0' and R='1' :-

       Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='0'.

            Nor-Gate-2 Output  : Q_n='1'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='1' and R='1'.

          Nor-Gate-1 Output  : Q='0'

       So, for S='0' and R='1' the SR Latch RESETS the output(ie,.output is set 

       to 0).This is called reset operation and to be used for clearing latched 

       data.

     Q='0' ,S='1' and R='0' :-

        Nor-Gate-2 :

          Nor-Gate-2 Input    : Q='0' and S='1'.

            Nor-Gate-2 Output  : Q_n='0'

       Nor-Gate-1 :

          Nor-Gate-1 Input    : Q_n='0' and R='0'.

          Nor-Gate-1 Output  : Q='1'

       So, for S='1' and R='0' the SR Latch SETS the output(ie., output is set 
       to 1). 

     Q='0' ,S='1' and R='1' :-

        Nor-Gate-2 :

         Nor-Gate-2 Input     : Q='0' and S='1'.

           Nor-Gate-2 Output   : Q_n='0'

       Nor-Gate-1 :

         Nor-Gate-1 Input     : Q_n='0' and R='1'.

         Nor-Gate-1 Output   : Q='0'

      Here both Q and Q_n is set to same logic level that is 0 .This is a 
       restricted combination or a forbidden state and it should never occur,it breaks
      the logic equation Q_bar=NOT Q. 

      Say, previously S='1' and R='1' --> output is Q='0' and Q_n='0'.

      and now its changed to S='0' and R='0' --> output is Q='1' and Q_n='1'.

      But this new output values will be looped back to input side               
      and this changes the output back to Q='0' and Q_n='0'.So, the 
      output will be oscillating,this oscillation will continue indefinitely 
      and will finally settle down at logic value 0 or 1.

Table :-
    Outputs for all combination of inputs and assumed values of Q.

    

 VHDL Code :

 entity SR_Latch is  
  Port ( S,R : in STD_LOGIC;  
         Q : inout STD_LOGIC;  
         Q_n : inout STD_LOGIC);  
 end SR_Latch;  
   
 architecture SR_Latch_arch of SR_Latch is  
 begin  
 process (S,R,Q,Q_n)  
       begin  
             Q <= R NOR Q_n;  
             Q_n <= S NOR Q;  
       end process;  
   
 end SR_Latch_arch;  
   

TCL Script [Xilix-ISim] For applying input Stimulus

Xilinx-ISim apply stimulus from tcl script (cont.):

Below is the code for a tcl script (ie.,stimulus.tcl) which when run in ISim CLI will apply input stimulus to get the output.The signal name ,duty cycle and period are the input parameters to be given in the script file .

please note that checks for validating input signal names,array bound and input signal value range are not kept .So,try to give valid values and signal name to get proper output otherwise no output will be generated.

How To Add inputs in Script File :

    Open the script file (ie.,stimulus.tcl) and go to "SIGNALS_TO_SET" procedure (search for "VARIABLES T0 SET" tag ).  

 ########################### VARIABLES T0 SET ###########################   
  #----------------------------------------------------------------------   
  # Imp Note : please check the syntax below    
  # Syntax : set <RetSigCnt> [AddSignal <signal_name> <Duty_cycle> <Period>]   
  #   
  # usage : for varying signals :: set RetSigCnt [AddSignal clock 50 20]   
  #   for constant signals :: set RetSigCnt [AddSignal enb_n $FORCE_ONE $CONST_PER]    
  #      
  proc SIGNALS_TO_SET {} {   
  global RetSigCnt   
  global FORCE_ZERO   
  global FORCE_ONE   
  global CONST_PER   
  ### !! ADD SIGNALS HERE !!:START###   
  set RetSigCnt  [AddSignal clock 50 20 ]   
  set RetSigCnt  [AddSignal Din 25 100 ]   
  set RetSigCnt   [AddSignal enb_n $FORCE_ZERO $CONST_PER ]    
  ### !! ADD SIGNALS HERE !!:END###   
  }   
  #---------------------------------------------------------------------   
  # TU : time unit    
  set TU      "ns"   
  set RunTime     1000   
  ########################### VARIABLES T0 SET ###########################   
  ########################################################################  

Now,go to "ADD SIGNALS HERE" to add input stimulus.

  ### !! ADD SIGNALS HERE !!:START###  
  set RetSigCnt   [AddSignal clock 50 20 ]  
  set RetSigCnt   [AddSignal Din  25 100 ]  
  set RetSigCnt    [AddSignal enb_n $FORCE_ZERO $CONST_PER ]   
  ### !! ADD SIGNALS HERE !!:END###  

Syntax :

  set <RetSigCnt> [AddSignal <signal_name> <Duty_cycle> <Period>]

<RetSigCnt>    -> return value count (it will tell number of signals added)
<signal_name>  -> input signal name (give valid input signal name)
<Duty_cycle>   -> duty cycle of the input signal.
                  100 (%) -> always 1
                  0   (%) -> always 0
                  50  (%) -> 50% time 1 and 50% time 0
<Period>       -> period of the input signal
AddSignal      -> This procedure will add entries to array.

Usage :

(1.)Suppose, enb_n is a signal and its a constant signal.

 set RetSigCnt [AddSignal enb_n $FORCE_ZERO $CONST_PER ]  

Then add the above line after "ADD SIGNALS HERE" statements (see above).
 FORCE_ONE   -> force signal to '1'
 FORCE_ZERO  -> force signal to '0'

(2.) Suppose,Din and clock are varying signal.

  set RetSigCnt   [AddSignal clock 50 20 ]  
  set RetSigCnt   [AddSignal Din  25 100 ]  

here clock name is "clock", clock duty cycle 50 % and clock period is 20 (ns).
D input signal name is "Din", Din duty cycle 25 % and clock period is 100 (ns).
Similary you can add any number of signals using AddSignal  procedure.

(3.) TU is time unit ,set to "ns"

(4.) RunTime is simluation run time length.

How to Run tcl script from Isim CLI :

source  <path>/<file-name>.tcl

Example : source  stimulus.tcl 

In this example the script file is located in project base directory.

Code : (stimulus.tcl)

 # This is a TCL script #  
  # File Name  : stimulus.tcl #  
  # Developer  : Sagar S  #  
  # Release   : REL_V_1  
  # Module name : Input stimulus generator for ISIM #  
  # How To run : source stimulus.tcl #  
  #       execute this command in Isim CLI#  
  #       and path to stimulus.tcl should be given#  
  #       if its in different directory #   
  #  
  ########################################################################  
  ########################### VARIABLES T0 SET ###########################  
  #----------------------------------------------------------------------  
  # Imp Note : please check the syntax below   
  # Syntax : set <RetSigCnt> [AddSignal <signal_name> <Duty_cycle> <Period>]  
  #  
  # usage : for varying signals :: set RetSigCnt [AddSignal clock 50 20]  
  #      for constant signals :: set RetSigCnt [AddSignal enb_n $FORCE_ONE $CONST_PER]   
  #       
  proc SIGNALS_TO_SET {} {  
  global RetSigCnt  
  global FORCE_ZERO  
  global FORCE_ONE  
  global CONST_PER  
  ### !! ADD SIGNALS HERE !!:START###  
  set RetSigCnt   [AddSignal clock 50 20 ]  
  set RetSigCnt   [AddSignal Din  25 100 ]  
  #set RetSigCnt       [AddSignal Din $FORCE_ONE $CONST_PER ]   
  ### !! ADD SIGNALS HERE !!:END###  
  }  
  #---------------------------------------------------------------------  
  # TU : time unit   
  set TU           "ns"  
  # Simulation Run Time  
  set RunTime         1000  
  ########################### VARIABLES T0 SET ###########################  
  ########################################################################  
  #***************** !Constant Variables! *****************#  
  #         Should not be changed         #  
  set HIGH     1  
  set LOW      0  
  set D       0  
  set T       0  
  array set SIGNAL  {}  
  set index      0   
  set RetSigCnt    0  
  set sigName     0   
  set FORCE_ONE    100  
  set FORCE_ZERO    0   
  set CONST_PER    1115558    
  ##########################################################  
 proc AddSignal {sigName duty_cycle period} {  
  global index  
  global SIGNAL  
  set i $index  
  set SIGNAL($i,$i,$i) "$sigName $duty_cycle $period"  
  set index [expr {$index+1}]  
  puts "ADDED Signal $index \n"  
  return $index  
 }  
 #__MAIN_FUNCTION__START  
 proc STIMULUS_SIM {} {  
 SIGNALS_TO_SET  
 global RetSigCnt  
 global HIGH  
 global LOW  
 global TU  
 global SIGNAL  
 for {set i 0} {$i < $RetSigCnt} {incr i} {  
   puts "$SIGNAL($i,$i,$i)"  
   set ii 1        
   foreach param $SIGNAL($i,$i,$i) {   
    #puts "param=$param"  
       if { $ii == 1} {  
        set sigName $param  
    } elseif { $ii == 2} {  
        set D  $param  
    } else {  
        set T  $param  
    }  
       set ii [expr {$ii + 1}]  
   }  
    #***************** Clock Generation *********************#  
    # T : signal period #  
    # D : duty_cycle is in % #   
       # if { $D == 100 } {  
        # set sigName $param  
    # }  
    set High_per    [expr {$D*$T/100}]  
    set Low_per    [expr {$T-$High_per}]  
    puts "sigName=$sigName ,High_per=$High_per and Low_per=$Low_per"  
    isim force add $sigName $LOW -value $HIGH -time $Low_per $TU -repeat $T $TU  
    #*********************************************************#  
 }  
 }  
 #__MAIN_FUNCTION__END  
 #__RESTART_SIM__START  
  proc RESTART_SIM {} {  
  puts "..Restarting Simulation.."  
  restart  
  }  
  #__RESTART_SIM__END  
  #__RUN_SIM__START  
  proc RUN_SIM { } {  
  global TU  
  global RunTime  
  puts "..Running Simulation For $RunTime $TU.."  
  run $RunTime $TU  
  }  
  #__RUN_SIM__END  
  #########################################################  
  ############## Main invoking method ####################  
  RESTART_SIM  
  STIMULUS_SIM  
  RUN_SIM   
  #########################################################  

You can also get this same code uploaded here.

If there is any Bug in this code please notify me

Basic Tcl commands

Tcl command Reference : http://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html
Online Tcl script editor :http://www.compileonline.com/execute_tcl_online.php

To check the tcl output please copy paste the below code in online tcl script editor and for more detailed explanation use the above reference .

(1.)Simple Text Output :
         puts "signal is not valid !!"
        puts stdout "error !!"

(2.)Assigning values to variables :
         set P "this is signal"
         set Q 12
         set R "1010101"  
        set S 18.881
        set M  $S
 

        puts "P=$P , Q=$Q"

        puts "bit vector is $R"

         puts "S=$S and M=$M"

(3.) Newline ,tab and backspace
         set P "\n \b this is signal\n"

        puts "Tab\tTab\tTab"
         puts "P=$P"

(4.) Grouping Statements using {}
         set LABLE "this is a sample msg"  

        puts "$LABLE"
         puts "$LABLE \t{$LABLE}"

(5.) Evaluation & Substitutions []
         set X  "abc"
         set Z  [set E "10101"]
   
         puts "\n X=$X  \n Z=$Z"

(6.) Results of a command: math functions,expr evaluation
         set x  1
         set p "this is signal"
         set yy [expr  { $x>0? ($x+1) : ($x-1) }]
         set tt [expr  { [string length $p]-2*$x }]
         set pi6 [expr {3.1415926/6.0}]
         set range  pow(2,6)
 
         puts "\n $yy \n $tt"
         puts "sin($pi6)=[expr {sin($pi6)}]"
         puts "range is $range"

(7.) Arithmetic operations
      Division :
         puts "1/2 is [expr {1/2}]"
        puts "-1/2 is [expr {-1/2}]"
        puts "1/2 is [expr {1./2}]" # . -> floating point rep.
        puts "1/3 is [expr {1./3}]" # . -> floating point rep.
         puts "1/3 is [expr {double(1)/3}]"

(8.) Comparisons 
     
     if-else :
          set X  1
          if {$X != 1}  {
                puts " X is not 1"
          } else {
       puts "X is 1"
     }

    else-if :
         set ii  2
       set k  "this is else-if clause"
       if { $ii == 1} {
             puts "1.k=$k"
       } elseif { $ii == 2} {
             puts "2.k=$k"
       } else {
            puts "3.k=$k"
      }

(9.) Looping statements
     
     while loop :
       set x 1
       while { $x < 8} {     
          set x [expr {$x + 1}]
if { $x == 3 } {
                 continue
} else {
                    puts "x =$x" 
}
        }
 
 For loop :
 example 1. 
           for {set i 0} {$i < 10} {incr i} {  # increment by 1
                   puts "i is $i"
            }
 example 2.
           for {set i 0} {$i < 10} {incr i 2} {  # increment by 2
                   puts "i is $i"
           }
 example 3.
           for {set i 0} {$i < 64 } {incr i} { 
              # generate all combination 6 bit binary number 
             # useful for random generation on inputs
            puts "\n"
            puts "[expr ($i & 0x20) >> 5] [expr ($i & 0x10) >> 4] [expr ($i & 
            0x08)>> 3] [expr ($i & 0x04) >> 2] [expr ($i & 0x02) >> 1] [expr $i
            & 0x01]"

        }

(10.) Arrays 
        example 1.
           array set val [list a 1 b 2 c 39]
          puts "$val(a)"
          puts "$val(b)"
          puts "$val(c)"
  
example 2.
        for {set i 0} {$i < 5} {incr i} { set a($i) $i }

        for {set i 0} {$i < 5} {incr i} { puts $a($i)  }
      
        example 3.
            array set val [list 2 "enb_n" 1 "din_1" 0 "din_0"] 
          puts "$val(2)"

        example 4.
            array set CODE-LIST [list  CODE-1   123 \
                                              CODE-2   678 \
                                              CODE-3   198 \
                                              CODE-4   "django unchained" \
                                              CODE-5   "The Matrix" ]
         puts  "$CODE-LIST(CODE-5)"
         >  The Matrix
         puts  "$CODE-LIST(CODE-1)"
         > 123

(11.) Adding new commands using proc
         proc add {arg1 arg2} {
set x  [expr {$arg1 + $arg2}];
return $x
        }
        set A 1
        set B 2

        puts "A+B=[add $A $B]"


 For Tcl tutorial Part-2 click here

How To Execute TCL script in Xilinx-ISIM CLI

Xilinx-ISim apply stimulus from tcl script :

Xilinx-ISim allows us to run tcl script from its CLI.The input stimulus to be generated and output signals to be checked (ie.,show value <signal>) can given in tcl script.

File name : <file-name>.tcl

                Example : stimulus.tcl 

How to Run tcl script from Isim Cli :-

source  <path>/<file-name>.tcl

Example : source  stimulus.tcl 

In this example the script file is located in project base directory.

Below are some sample tcl scripts ,use and modify according to your needs.

Example 1.  

 This script will restart the simulation from time 0 ,adds input signals and runs the simulation .Open a file in text editor and save it with tcl extension (ie., stimulus.tcl) and then copy paste the below code.

  # This is a TCL script #  
  # File Name : stimulus.tcl #  
  # How To run : source stimulus.tcl #  
  #       execute this command in Isim CLI#  
  #       and path to stimulus.tcl should be given#  
  #       if its in different directory #   
  puts "..restarting simulation.."  
  restart  
  puts "..inserting input stimulus.."  
  isim force add s 0 -value 1 -time 50 ns -repeat 100 ns  
  isim force add r 1 -value 0 -time 100 ns -repeat 200 ns  
  isim force add clock 0 -value 1 -time 20 ns -repeat 40 ns  
  puts "..running simulation.."  
  run  

Example 2.
  see this Link

Xilinx-ISim useful CLI Commands

How to Display a value :-

Syntax : show value <signal or variable name>

Example 1. 
                show value clk
                It will display clk signal value at current simulation time.

Example 2.  
                   show value addrs
               It will display the 32bit address
                
Example 3.  
                    show value addrs -radix hex
                It will display the 32bit address in hexadecimal.
                other radixes - dec/hex/bin/oct/default

Example 4.
                  signal vect: std_logic_vector(0 to 5)
               show value vect(0) 
               Displays 0th position in vect (vector of std_logic).

               show value vect(1:2)
               Displays slice of vect from 1 to 2

               show value vect
               Displays entire vector vect.


How to Test a Signal :-

Test command is used for comparing a signal with a value.If condition is true
returned value is 1 else 0 is returned. 

Syntax          : test <signal>  <value>
Return value   : true  '1'
                     false '0' 

Example 1.
                   signal reg : std_logic_vector(15 downto 0)
                   test module_1/reg(5)    1
               It compares bit in position 5 of reg signal in module module_1 that
               is instantiated under your current scope.

Example 2.
                   test A FF -radix hex 
                To compare the value of signal A to FF.

Example 3.
                   test clk '0'                
                To compare value '0' with clk value.

Example 4.
                   signal vect: std_logic_vector(7 downto 0)
                   test vect 101010
                   To compare vect value with "101010".

Isim Put command :-
  Put command will allow to change the value of the signal on run time.
 Syntax         : put <signal>  <value>

 Example 1.
                   put clk 1
                  or
                   put clk 1 -radix bin
                  or
                   put clk "1" -radix bin
                This will set clk to 1 on runtime.
 Example 2.
                   signal slv: std_logic_vector(4 downto 0)
                put slv 01010
                To assign a value "01010" to signal slv.

 Example 3.
                   put A FF -radix hex
                To assign a value FF to signal A.

How To Set a Signal :-

ISIM FORCE Cmd  
Syntax : isim force (add|remove) < object_name > < value > [options]

1. isim force add enb_n 0 force enb_n signal to zero.
 
2. isim force add reset 1 -time 10 ns -cancel 50 ns force reset to 1 at 10 ns and cancel after 50ns.

3. isim force add clock 0 -value 1 -time 10 ns -repeat 20 ns
At t=0 ns clock='0'
At t=10 ns clock='1' 
and repeat this every 20 ns.
Syntax :
 isim force add <signal-name> <LOW/HIGH> -value <HIGH/LOW> 
-time <LOW-Period/HIGH-Period> -repeat <Total-Period>

4. isim force add din 0 -value 1 -time 10 ns -value 0 -time 30ns 
-repeat 100 ns

  5. isim force remove enb_n
      isim force remove reset 
     To remove the values on signal enb_n and reset.

Other Commands :-
   
 1.  isim get userunit
        returns current unit of time (default is ps).
   
 2.  isim ltrace on/off
        ltrace command lets you turn line tracing on or off.

 3.  isim ptrace on/off
         ptrace command lets you turn process tracing on or off. When turned on,
    the command also displays the name of the currently executing VHDL  
    process in the Simulation Console tab. 

 4. run command :-
     
     run 2000ns  : runs the simulation for 2000ns.
     run 1.2ns    : runs the simuation for 1.2ns.
     run all         : runs simulation until all events are executed.
     run             : runs till the step size given in isim window.  

 5. isim  set  radix  <radix-type>
      radix types : default, dec,bin, oct, hex, unsigned and ascii.

 6. step
        To step through one line of HDL code.  

VHDL History

History :

VHDL is an acronym for very high speed integrated circuit language (VHSIC) hardware description language (HDL). VHDL is used to describe the logical structure and functions of digital systems that are varying from simple gates to complex PLDs (FPGAs, ASICs). It facilitates design specification and simulation of digital systems. Even though initially it was not meant for synthesis, it can be used for synthesis within a limited domain. 

It was initiated by the US Department of Defense in the 1980s as a need for a standard HDL for their projects as different vendors were using different languages for IC design. In 1981, three companies —IBM, Texas Instruments and Intermetrics—were entrusted with the job of developing a common standard language for design, and VHDL was proposed as the high description language.Presently, Verilog and VHDL are two design HDLs used widely.

Design :

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.
VHDL is strongly typed and is not case sensitive.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. 
It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.

Advantages:

The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system.

A VHDL project is portable.

Disadvantages:

lack of analog support.

VHDL Simulators available:

Commercial:
Aldec Active-VHDL
Cadence Incisive 
Mentor Graphics ModelSim.
Synopsys VCS
Xilinx Vivado 

Other:
GHDL and GTKWave
Simili

Shift Operators in VHDL

vect   = 1 0 X 1 Z       
result  = 0 0 0 0 0 (initialized to 0)

SLL : (Shift Left Logical)

  result <= vect sll 1  
  output :  vect  = 1 0 X 1 Z  
               result = 0 X 1 Z 0  
  In SLL LSB bit is filled 0.   

SRL : (Shift Right Logical)  

    result <= vect srl 1  
  output :  vect    = 1 0 X 1 Z   
               result   = 0 1 0 X 1  
      In SRL MSB bit is filled 0.  

SLA : (Shift Left Arithmetic)

  Example 1.  
    result <= vect sla 1  
    output :   vect    = 1 0 X 1 Z  
                  result   = 0 X 1 Z Z  
     In SLA LSB bit is replicated.  
 Example 2.  
    result <= vect sla 2  
    output :  vect   = 1 0 X 1 Z  
                 result  = X 1 Z Z Z  
    In SLA LSB bit is replicated twice (ie.,no of shifts).  

SRA : (Shift Right Arithmetic)

   Example 1.  
     result <= vect sra 1  
     output : vect   = 1 0 X 1 Z  
                 result  = 1 1 0 X 1  
     In SRA MSB bit is replicated.  
  Example 2.  
     result <= vect sra 2  
     output : vect   = 1 0 X 1 Z  
                 result  = 1 1 1 0 X  
     In SRA MSB bit is replicated twice (ie.,no of shifts).  

ROL : (Rotate Left)

    result <= vect rol 2  
  output : vect   = 1 0 X 1 Z  
              result  = 1 Z 1 0 X  

ROR : (Rotate Right)

    result <= vect ror 2  
  output : vect   = 1 0 X 1 Z  
              result  = X 1 Z 1 0  

More Examples :

Example 1. 
    vect   = 0 1 1 0  -> (6)
    result = 0 0 0 0  -> (initializedto 0)
    All are Shift by 1 unit operation.

    SLL :
    vect SLL 1        result       actualResult
    (mul by 2)
    1 1 0 0           12(C)          12
    1 0 0 0           8 -error-      24 
    0 0 0 0           0                0
   
    SLL does multiplication operation by 2^(no.Shifts).In case of error in multiplication result add a correction bit of 2^(n-1) (where n is no. of bits needed for representing the actual result) at MSB.
   i.e., 2^4 * 1+ 2^3 * 1 + 0 + 0 + 0  = 24 is the actual result.

    SRL :
    vect SRL 1        result       actualResult
    (div by 2)
     0 0 1 1          3               3
     0 0 0 1          1 -error-     1.5
     0 0 0 0          0               0

    SRL does Division operation by 2^(no.Shifts).In case of error in division result add (2^-m) (Where m is number of correction bit needed) at LSB to get the actual result. 
   i.e., 0 + 0 + 0 +1*2^0 + (2^-1) = 1 + 0.5 = 1.5 

Example 2.
   vect   = 1 1 1 1  ->(15)
   result = 0 0 0 0  ->(initialized to 0)

   All are Shift by 1 unit operation.
   SLL :
   vect SLL 1    result   actual      #bits to Rep.      Binary Rep Of    
   (mul by 2)                   Result      Actual Result     Actual Result            
    1 1 1 0         14(E)    30          5 bits (0 -31)      1 1 1 1 0       
    1 1 0 0         12(C)    60          6 bits (0 -63)      1 1 1 1 0 0    
    1 0 0 0         8          120        7 bits (0-127)     1 1 1 1 0 0 0
    0 0 0 0         0          0           4 bits                 0 0 0 0

    #of Correction           Correction Bits
    Bits    
    5-4=1              2^4 *1 + 2^3 *1 + 2^2 *1 + 2^1 *1 + 0 = 30
    6-4=2              2^5 *1 + 2^4 *1 + 2^3 *1 + 2^2 *1 + 0 + 0 = 60
    7-4=3              2^6 *1 + 2^5 *1 + 2^4 *1 + 2^3 *1 + 0 + 0 + 0 = 120
    4-4=0              0 + 0 + 0 + 0 = 0

   SRL :
    vect SRL 1        result          actual        
    (div by 2)                               Result     
    0 1 1 1             7 (odd)      7.5      
    0 0 1 1             3 (odd)      3.75     
    0 0 0 1             1 (odd)      1.875    
    0 0 0 0            0               0   
  
    #of Correction                Correction Bits
     Bits=m       
    1     0 + 2^2 *1 + 2^1 *1 + 2^0 *1 +2^-1 *1 = 7.5
    2                  0 + 0 + 2^1 *1 + 2^0 *1 + 2^-1 *1 + 2^-2 *1 = 3.75
    3     0 + 0 + 0 + 2^0 *1 + 2^-1 *1 + 2^-2 *1 +2^-3 *1= 1.875
    0     0 + 0 + 0 +0 = 0